Increased Light Extraction of Thin-Film Flip-Chip UVB LEDs by Surface Texturing

Ultraviolet light-emitting diodes (LEDs) suffer from a low wall-plug efficiency, which is to a large extent limited by the poor light extraction efficiency (LEE). A thin-film flip-chip (TFFC) design with a roughened N-polar AlGaN surface can substantially improve this. We here demonstrate an enabling technology to realize TFFC LEDs emitting in the UVB range (280–320 nm), which includes standard LED processing in combination with electrochemical etching to remove the substrate. The integration of the electrochemical etching is achieved by epitaxial sacrificial and etch block layers in combination with encapsulation of the LED. The LEE was enhanced by around 25% when the N-polar AlGaN side of the TFFC LEDs was chemically roughened, reaching an external quantum efficiency of 2.25%. By further optimizing the surface structure, our ray-tracing simulations predict a higher LEE from the TFFC LEDs than flip-chip LEDs and a resulting higher wall-plug efficiency.

shows the epitaxial structure of the TFFC LEDs which was grown by metalorganic vaporphase epitaxy in a close-coupled shower head reactor and the doping was achieved using silane (SiH 4 ) as an n-dopant and cyclopentadienylmagnesium (Cp 2 Mg) as a p-dopant. In a first step, a pseudosubstrate was grown on a c-plane AlN/sapphire substrate with a relaxed Al 0.5 Ga 0.5 N toplayer [1]. To later enable substrate removal, a 235 nm Al 0.5 Ga 0.5 N:Si current spreading layer for the electrochemical etching was grown. After that a multilayered sacrificial layer comprising a 118-nm thick Al 0.37 Ga 0.63 N layer and a five-period structure of alternating 5-nm thick Al 0.11 Ga 0.89 N and 5-nm thick Al 0.37 Ga 0.63 N was grown in between two Al 0.50 Ga 0.50 N etch block layers with a thickness of 207 nm and 475 nm respectively. Whereas the top etch block layer is unintentionally doped, the bottom etch block layer has an n-doping level of 0.5 × 10 18 cm −3 to enable current flow to the sacrificial layer. The Si concentration in the sacrificial layer was 2 × 10 19 cm −3 for all layers. On top of the sacrificial layer and etch block layer, the LED heterostructure was grown. This consisted of a 1200-nm-thick n-doped Al 0.5 Ga 0.5 N current spreading layer (Si concentration: 2 × 10 18 cm −3 )) followed by a threefold InAlGaN MQW active region, a 25nm-thick Al 0 The fabrication process started with the definition of the device mesa using Cl-based dry etching. The etching depth was chosen to fully expose the sacrificial layer. This was followed by a second dry etching step to define the lateral extent of the active region and to expose the n-side of the LED. Two different mesa shapes, a rectangular mesa and an interdigitated mesa, were fabricated to investigate the lateral current spreading and carrier injection. The V/Al/Ni/Au (15/90/20/30 nm) n-contact was evaporated and annealed for 40 s at 800 • C in an N 2 atmosphere [2]. In the same process step, also the contact for applying the bias voltage during the electrochemical etching was formed. After that, a Pd/Al/Ni/Au (3/150/100/100 nm) p-contact was evaporated on the p-AlGaN. To improve the planarity of the devices for the bonding, the n-and p-contacts were leveled using a Ti/Au metal pad on the n-contact. Both contacts were finished by Ti/Au (10/600 nm) bondpads to provide a base for the thermocompression bonding. In the next step, a 500-nm thick SiO 2 layer was deposited by reactive sputtering and patterned using Ar/CHF 3 -based dry etching (see Fig. S2(a)). This dielectric layer promoted unidirectional lateral electrochemical etching, acted as a tether to keep the thin-film LEDs in place after the sacrificial layer removal and served as an insulation layer to prevent short-circuiting after the flip-chip bonding.
Before the sacrificial layer removal, a 3.5 µm-thick photoresist layer was deposited to protect the surface of the devices, especially the n-contact, from parasitic etching during the electrochemical etching. The thick resist layer further supports the SiO 2 tethers to keep devices in place. Figure S2(c) shows an LED at this stage, just before the electrochemical etching. The sacrificial layer was then laterally etched using a bias voltage of 15 V vs. a graphite rod in 0.3 M nitric acid. The etching was done at room temperature and the electrolyte was stirred using a magnetic stir bar without intentional illumination. The etching process was intentionally started from one corner of the device to proceed unidirectionally from this point beneath the device. The progress of the etching was monitored in-situ using an optical microscope to time the etching. After the complete removal of the sacrificial layer, the sample was immersed in de-ionized water to remove acid residues, followed by acetone and isopropanol cleaning. These solvents removed the resist protection and reduced the force on the membrane during the subsequent drying in air. After the cleaning process, the thin-film LEDs were held by the SiO 2 tether layer, see Fig. S2(d), which surrounds the device mesa. Because the tether area depends on the device perimeter, one group of devices included fins to increase the perimeter as shown in Fig. S2(b). Figure S2(e) shows a schematic cross-section of the carrier chip onto which the thin-film LEDs were bonded. The carrier chip had electroplated Au-pillars of a height of 3 µm and diameter of 15 µm, which were arranged in a hexagonal pattern with a pitch of 30 µm. These pillars for the bonding were used instead of continuous large-area bonding pads to facilitate deformation and adaption during the thermocompression bonding [3]. Ti/Au metal lines were used to connect to the LEDs, which were electrically separated by the SiO 2 -on-Si substrate and a SiO 2 layer on the top to further prevent potential shortcircuiting of the LEDs after the flip-chip bonding.
Both the LED chips and the carrier chips were cleaned by UV-ozone to remove organic residues before the bonding. The thermocompression bond was accomplished under a mechanical pressure of around 100 MPa for 1 hour at 300 • C in ambient air. After the bonding, during which the SiO 2 tethers break, the growth substrate of the UV LED is separated from the carrier chip while the single LEDs remain bonded to the carrier chip.
Individual LEDs were selectively roughened to investigate the impact of different degrees of roughness on the device performance. The lithography was selectively done using direct laser writing using a 5.3 µm-thick positive photoresist to avoid parasitic etching of other devices and device parts, especially the bonding and contact metal layer, during the roughening step. Because the TMAH-based developer (Microdeposit MF-CD-26) for the photoresist etches the N-polar AlGaN surface, a PMMA interlayer was spun before the photoresist to separate development and roughening. Therefore, after the resist development which stopped on the PMMA surface, O 2 plasma was used to remove the PMMA layer in the open area. These open areas were then exposed to the developer at room temperature for 9 minutes for one group of LEDs and 15 minutes for another group. After the roughening, the resist was stripped in solvents and O 2 plasma.

S3
Supplementary Note 3: I-V characteristics Figure S3: I-V-characteristics of an LED after bond pad fabrication and after sacrificial layer removal and transfer.